Semiconductor memory device

ABSTRACT

The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area. Therefore, it is possible to prevent the thickness of the element separation insulating film of high voltage withstanding area from being thinned and prevent reliability of the memory cell from being reduced.

This application is a divisional of application Ser. No. 08/570,574, filed Dec. 11, 1995 U.S. Pat. No. 5,658,812.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memory device which is operated by a plurality of power source voltages such as a voltage at the time of reading data like a nonvolatile semiconductor memory, and a higher voltage at the time of writing and erasing data, and its manufacturing method.

2. Description of the Related Arts

In a nonvolatile semiconductor memory device, data writing and erasing operations are performed by a high voltage. On the other hand, a normal reading operation is performed by a low voltage as compared with the writing and erasing operations. Due to this, a thick gate insulating film, which can withstand a high voltage, is needed in the elements used in writing and erasing in order to ensure reliability. In contrast, since a lower voltage is needed in the elements used in reading, a thin gate insulating film may be used. Rather, there is a case in which the thin gate insulating film may be used in order to achieve a high performance such as a high speed operation.

Therefore, there is a case in which it is necessary to have two or more kinds of different thickness gate insulating films and element separation insulating films formed in one device.

FIGS. 28 to 32 are cross sectional views showing a conventional method for manufacturing a nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device includes a high voltage withstanding transistor area (hereinafter called "high voltage withstanding area"), transistor areas other than the high voltage withstanding area ("low voltage withstanding area"), and a memory cell transistor area (hereinafter called "cell area").

First, as shown in FIG. 28, first to sixth element separation insulating films 2a to 2f are formed on a surface of a p type silicon substrate 1 having a cell area 1a, a high voltage withstanding area 1b and a low voltage withstanding area 1c. An oxide-nitride film 3 having a thickness of about 100 angstroms to serve as a gate insulating film of the cell area 1a is formed on the surface of the p type silicon substrate 1 positioned among these element separation insulating films 2a to 2f. Thereafter, a first polycrystalline silicon film 4 is deposited on these element separation insulating films 2a to 2f and the oxide-nitride film 3.

Next, as shown in FIG. 29, a first resist pattern 5 is formed on the first polycrystalline silicon film 4. Thereafter, the first resist pattern 5 is used as a mask to perform etching, whereby the first polycrystalline silicon film 4 positioned on a floating gate separation area 6 of the cell area 1a is removed.

Thereafter, as shown in FIG. 30, the first resist pattern 5 is separated. Next, an ONO (oxide-nitride-oxide) layer film 7, serving as an insulating film between a control gate and a floating gate, is formed on a surface of said first polycrystalline silicon film 4.

Next, as shown in FIG. 31, a second resist pattern 8 is formed on the cell area 1a. Thereafter, the resist pattern 8 is used as a mask to perform etching, whereby the ONO layer film 7 and the first polycrystalline silicon film 4 are removed. Next, the oxide-nitride film 3, which is positioned on each of the high voltage withstanding area 1b and the withstanding low voltage area 1c, is etching-removed with NH₄ F, thereby exposing the surface of the p type silicon substrate 1.

Thereafter, as shown in FIG. 32, the second resist pattern 8 is separated. Next, an oxide film 9 having a thickness of about 250 angstroms to serve as a gate insulating film of the high voltage withstanding area 1b is formed on the surface of the exposed p type silicon substrate 1.

Thereafter, a second polycrystalline silicon film 10 is deposited on each of the ONO layer film 7, the third to sixth element separation insulating films, and the oxide film 9.

In the above-mentioned conventional nonvolatile semiconductor memory device and its manufacturing method, the third and fourth element separation insulating films 2c and 2d, which are positioned at the high voltage withstanding area 1b, become thin. This is because the third and fourth element separation insulating films 2c and 2d are simultaneously etched when the oxide-nitride film 3 is etched as shown in FIG. 31. As a result, a reverse field voltage is lowered in the third and fourth element separation insulating films 2c and 2d, and there occurs a problem in providing a required high withstanding voltage to the high voltage withstanding area 1b.

As a method for preventing the reverse field voltage from being lowered, it can be considered that thick impurity material is implanted to the p type silicon substrate 1, which is positioned just under the third and fourth element separation insulating films 2c and 2d. However if this method is used in a minute element, deterioration of the narrow channel effect of the transistor occurs by exudation of impurity material, and a reduction of withstanding voltage of the surface of the high voltage withstanding element occurs. Therefore, the above-mentioned problem cannot be solved by this method.

Moreover, in the process of exposing the surface of the p type silicon substrate 1 of each of the high voltage withstanding area 1b and the low voltage withstanding area 1c, as shown in FIG. 31, the second resist pattern 8 is directly formed on the ONO layer 7 film of the cell area 1a. Due to this, the ONO layer film 7 is polluted by the resist, and the film quality of the ONO layer film 7 is deteriorated. Due to the polluted ONO layer film 7, there are problems in insulation breakage of the nonvolatile semiconductor memory device and deterioration of data storing characteristics. As a result, reliability of the memory cell is lowered.

Furthermore, since the oxide nitride film 3 is used as a gate insulating film of the memory cell transistor in accordance with a requirement for high voltage withstanding and high reliability, a white ribbon (SiN), which is not fully removed, is left on the surface of the p type silicon substrate 1 of each of the high voltage withstanding area 1b and the low voltage withstanding area 1c when the film 3 is etching-removed. The white ribbon becomes a problem particularly in the high voltage withstanding area 1b. More specifically, by the white ribbon, as shown in FIG. 32, the withstanding voltage of the gate insulating film 9 formed in the high voltage withstanding 1b is deteriorated, and breakage of the insulating film is caused when the high voltage is applied to the gate insulating film 9. Then, reduction of yield occurs.

SUMMARY OF THE INVENTION

In consideration of the above-mentioned problems, the present invention has been made, and an object of the present invention is to provide a nonvolatile semiconductor memory device and manufacturing method in which both thinning of the thickness of an element separation insulating film of a high voltage withstanding area and a reduction of reliability of a memory cell are prevented.

In order to solve the above problems, the present invention includes a first element separation insulating film for separating an area forming a first MOS transistor where a first power voltage is applied and a second element separation insulating film for separating an area forming a second MOS transistor where a second power voltage higher than the first power voltage is applied, and having a thickness larger than the thickness of the first element separation insulating film.

Moreover, the present invention includes a first polycrystalline silicon film for forming a part of a gate electrode in a first MOS transistor where a first power voltage is applied, and a second polycrystalline silicon film for forming a part of a gate electrode in a second MOS transistor where a second power voltage higher than the first power voltage is applied, having a thickness larger than the thickness of the first polycrystalline silicon film.

Furthermore, various embodiments of the present invention include the steps of: forming, on a surface of a semiconductor substrate, a first element separation insulating film for separating a first area forming a first MOS transistor where a first power voltage is applied, a second element separation insulating film for separating a second area forming a second MOS transistor where a second power voltage higher than the first power voltage is applied, and a third element separation insulating film for separating a third area forming a memory cell transistor; forming a first oxide film serving as a gate insulating film of the second MOS transistor on the surface of the semiconductor substrate; depositing a first polycrystalline silicon film on the first oxide film and the first to third element separation insulating films; forming a first resist pattern on the first polycrystalline silicon film of each of the first and second areas; etching the first polycrystalline silicon film of the third area using the first resist pattern as a mask; removing the first oxide film from the third area after separating the first resist pattern; forming a second oxide film, serving as a gate insulating film of the memory cell transistor, on a surface of the semiconductor substrate on the third area; depositing a second polycrystalline silicon film, serving as a floating gate of the memory cell transistor, on the second oxide film; introducing impurity material to the second polycrystalline silicon film; forming a second resist pattern on the second polycrystalline silicon film on an area of each of the second and third areas where a floating gate electrode is formed; etching the second polycrystalline silicon film using the second resist pattern as a mask; forming a first insulating film serving as an insulating film between a floating gate of the memory cell transistor and a control gate, on the second polycrystalline silicon film after separating the second resist pattern; depositing a third polycrystalline silicon film on the first insulating film; forming a third resist pattern on the third polycrystalline silicon film on the third area; etching the third polycrystalline silicon film from the first and second areas using the third resist pattern as a mask; etching the first insulating film of the first and second areas using the third resist pattern as a mask; etching the first polycrystalline silicon film from the first area and the second polycrystalline silicon film on the second area using the third resist pattern as a mask; etching the first oxide film from the first area after separating the third resist pattern; forming a third oxide film, serving as a gate insulating film of the first MOS transistor, on a surface of the semiconductor substrate on the first area on a surface of the first polycrystalline silicon film on the second area, and on a surface of the third polycrystalline silicon film on the third area; depositing a fourth polycrystalline silicon film on the third oxide film; forming a fourth resist pattern on the fourth polycrystalline silicon film of the first area; etching the fourth polycrystalline silicon film using the fourth resist pattern as a mask; and depositing a fifth polycrystalline silicon film on the first to third areas after separating the fourth resist pattern.

Furthermore, various embodiments of the present invention include the steps of: forming on a surface of a semiconductor substrate, a first element separation insulating film for separating a first area forming a first MOS transistor where a first power voltage is applied, a second element separation insulating film for separating a second area forming a second MOS transistor where a second power voltage higher than the first power voltage is applied, and a third element separation insulating film for separating a third area forming a memory cell transistor; forming a first oxide film, serving as a gate insulating film of the second MOS transistor, on a surface of the semiconductor substrate; depositing a first polycrystalline silicon film on the first oxide film and the first to third element separation insulating films; forming an oxide film on the first polycrystalline silicon film; forming a first resist pattern on the oxide film on each of the first and second areas; etching the oxide film and the first polycrystalline silicon film using the first resist pattern as a mask; removing the first oxide film from the third area after separating the first resist pattern; forming a second oxide film, serving as a gate insulating film of the memory cell transistor, on a surface of the semiconductor substrate of the third area; depositing a second polycrystalline silicon film, serving as a floating gate of the memory cell transistor, on the second oxide film; introducing impurity material to the second polycrystalline silicon film; forming a second resist pattern on the second polycrystalline silicon on the third area where the floating gate electrode is formed and on the second area; etching the second polycrystalline silicon film using the second resist pattern as a mask; forming a first insulating film, serving as an insulating film between the floating gate of the memory cell transistor and a control gate, on the second polycrystalline silicon film after separating the second resist pattern; depositing a third polycrystalline silicon film on the first insulating film; forming a third resist pattern on the third polycrystalline silicon film on the third area; etching the third polycrystalline silicon film from the first and second areas using the third resist pattern as a mask; etching the first insulating film of the first and second areas using the third resist pattern as a mask; etching the first polycrystalline silicon film from the first area and the second polycrystalline silicon film of the second area in a state that the third resist pattern is used as a mask; and introducing impurity material to the semiconductor substrate using the third resist pattern.

Furthermore, various embodiments of the present invention include the steps of: forming, on a surface of a semiconductor substrate, a first element separation insulating film for separating a first area forming a first MOS transistor where a first power voltage is applied, a second element separation insulating film for separating a second area forming a second MOS transistor where a second power voltage higher than the first power voltage is applied, and a third element separation insulating film for separating a third area forming a memory cell transistor; forming a first oxide film, serving as a gate insulating film of the second MOS transistor, on a surface of the semiconductor substrate; depositing a first polycrystalline silicon film having a thickness sufficient for a mask, when introducing impurity material to the semiconductor substrate of the first area in a later process, on the first oxide film and the first to third element separation insulating film; forming a first resist pattern on the oxide film of each of the first and second areas; etching the first polycrystalline silicon film using the first resist pattern as a mask; removing the first oxide film of the third area after separating the first resist pattern; forming a second oxide film, serving as a gate insulating film of the memory cell transistor, on a surface of the semiconductor substrate on the third area; depositing a second polycrystalline silicon film, serving as a floating gate of the memory cell transistor, on the second film; introducing impurity material into the second polycrystalline silicon film; forming a second resist pattern on the second polycrystalline silicon film on the third area where a floating gate electrode is formed and on the second area; etching the second polycrystalline silicon film using the second resist pattern as a mask; forming a first insulating film, serving as an insulating film between a floating gate of the memory cell transistor and a control gate, on the second polycrystalline silicon film after separating the second resist pattern; depositing a third polycrystalline silicon film on the first insulating film; forming a third resist pattern on the third polycrystalline silicon film on the third area; etching the third polycrystalline silicon film from the first and second areas using the third resist pattern as a mask; etching the first insulating film from the first and second areas using the third resist pattern as a mask; using the third resist pattern, the first polycrystalline silicon film, and the silicon oxide film as a mask to introduce impurities into the first area; and etching the first polycrystalline silicon film from the first area and the second polycrystalline silicon film of the second area using the third resist pattern as a mask.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the present invention will become apparent during the following discussion in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross sectional view showing a method for manufacturing a nonvolatile semiconductor memory device of a first, second, or third embodiment of the present invention;

FIG. 2 shows a method for manufacturing a nonvolatile semiconductor memory device of the first or third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 1;

FIG. 3 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 2;

FIG. 4 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 3;

FIG. 5 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 4;

FIG. 6 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 5;

FIG. 7 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 6;

FIG. 8 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 7;

FIG. 9 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 8;

FIG. 10 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 9;

FIG. 11 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 10;

FIG. 12 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 11;

FIG. 13 shows a method for manufacturing a nonvolatile semiconductor memory device of the first embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 12;

FIG. 14 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 1;

FIG. 15 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 14;

FIG. 16 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is cross sectional view showing a process next to FIG. 15;

FIG. 17 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 16;

FIG. 18 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 17;

FIG. 19 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 18;

FIG. 20 shows a method for manufacturing a nonvolatile semiconductor memory device of the second embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 19;

FIG. 21 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 2;

FIG. 22 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 21;

FIG. 23 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 22;

FIG. 24 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 23;

FIG. 25 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention and is a cross sectional view showing a process next to FIG. 24;

FIG. 26 shows a method for manufacturing a nonvolatile semiconductor memory device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 25;

FIG. 27 shows a method for manufacturing a nonvolatile semiconductor device of the third embodiment of the present invention, and is a cross sectional view showing a process next to FIG. 26;

FIG. 28 is a cross sectional view showing a conventional method for manufacturing a nonvolatile semiconductor memory device;

FIG. 29 shows a conventional method for manufacturing a nonvolatile semiconductor memory device, and is a cross sectional view showing a process next to FIG. 28;

FIG. 30 shows a conventional method for manufacturing a nonvolatile semiconductor memory device, and is a cross sectional view showing a process next to FIG. 29;

FIG. 31 shows a conventional method for manufacturing a nonvolatile semiconductor memory device, and is a cross sectional view showing a process next to FIG. 30;

FIG. 32 shows a conventional method for manufacturing a nonvolatile semiconductor memory device, and is a cross sectional view showing a process next to FIG. 31.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments of the present invention will be described below in detail, with reference being made to the accompanying drawings.

FIGS. 1 to 13 are cross sectional views showing a method for manufacturing a nonvolatile semiconductor memory device of a first embodiment of the present invention. This nonvolatile semiconductor memory device is a flash EEPROM in which an area having a high voltage withstanding MOS transistor to which high voltage (e.g., 12 v) is applied at the time of writing and erasing (hereinafter called "high voltage withstanding area"), an area having other MOS transistors to which no high voltage (e.g., 5-3.3 v) is applied (hereinafter called "low voltage withstanding area"), and an area where a memory cell transistor is formed which, e.g., 10 v is applied when writing and erasing mode, 3 v is applied when reading mode (hereinafter called "cell area") are provided (hereinafter called as "cell area") on the same substrate.

First, as shown in FIG. 1, first to sixth element separation insulating films 12a to 12f are formed on a surface of a p type silicon substrate 11 having a cell area 11a, a high voltage withstanding area 11b, and a low voltage withstanding area 11c.

As shown in FIG. 2, a silicon oxide film 13, serving as a gate insulating film of the high voltage withstanding area 11b and having a thickness of about 250 angstroms, is formed on the surface of the p type silicon substrate 11 positioned among first to sixth separation insulating films 12a to 12f.

Thereafter, a first polycrystalline silicon film 14 having a thickness of about 1000 angstroms is deposited on the first to sixth element separation insulating films 12a to 12f and the silicon oxide film 13 by LPCVD.

Thereafter, as shown in FIG. 3, a first resist pattern 15 is formed on the first polycrystalline silicon film 14 by lithography, and the resist is positioned on each of the high voltage withstanding area 11b, and the low voltage withstanding area 11c. Then, the first resist pattern 15 is used as a mask to perform isotropic etching, thereby removing the first polycrystalline silicon film 14 from the cell area 11a.

Next, as shown in FIG. 4, the first resist pattern 15 is removed. Thereafter, the silicon oxide film 13 is removed from the cell area 11a by etching using NH₄ F, thereby exposing a surface of the p type silicon substrate 11.

Thereafter, as shown in FIG. 5, an oxide-nitride film 16 having a thickness of about 100 angstroms to serve as a gate insulating film of the cell area 11a is formed on the surface of the exposed p type silicon substrate 11. At this time, an oxide-nitride film 16a is formed on the first polycrystalline silicon film 14 of the high voltage withstanding area 11b, and an oxide-nitride film 16b is formed on the first polycrystalline silicon film 14 of the low voltage withstanding area 11c. Then, a second polycrystalline silicon film 17 having a thickness of about 1000 angstroms to serve as a floating gate of the cell area 11a is deposited on the oxide-nitride films 16, 16a, and 16b, and the first and second element separation insulating films 12a and 12b. Thereafter, phosphorus is doped to the second polycrystalline silicon film 17 by phosphorus diffusion.

Then, as shown in FIG. 6, a second resist pattern 18 is formed on the second polycrystalline silicon film 17. The second resist pattern 18 is positioned at an area 19 where the floating gate of the cell transistor is formed and on the high voltage withstanding area 11b. Thereafter, the second resist pattern 18 is used as a mask to perform etching, whereby the second polycrystalline silicon film 17 on each of a floating gate separation area 20 of the cell area 11a and the low voltage withstanding area 11c is removed.

Thereafter, as shown in FIG. 7, the second resist pattern 18 is removed. Then, as an insulating film between the floating gate of the cell transistor and a control gate, for example, an ONO (oxide-nitride-oxide) layer film 21 is formed on the second polycrystalline silicon film 17 of the cell area 11a. At this time, an ONO layer film 21a is formed on the second polycrystalline silicon film 17 of the high voltage withstanding area 11b, and an ONO layer film 21b is formed on the first polycrystalline silicon film 14 of the low voltage withstanding area 11c. Thereafter, a third polycrystalline silicon film 22 having a thickness about 1000 angstroms is deposited on the ONO layer films 21, 21a and 21b.

Next, as shown in FIG. 8, a third resist pattern 23 is formed on a third polycrystalline silicon film 22 of the cell area 11a. Thereafter, the resist pattern 23 is used as a mask to perform isotropic etching, so that the third polycrystalline silicon films 22 of the high voltage withstanding area 11b and the low voltage withstanding area 11c are simultaneously removed.

Next, the third resist pattern 23 is used as a mask to perform anisotropic etching, thereby removing the ONO layer films 21a and 21b. Thereafter, the resist pattern 23 is used as a mask to perform etching, so that the second polycrystalline silicon film 17 of the high voltage withstanding area 11b and the first polycrystalline silicon film 14 of the low voltage withstanding area 11c are simultaneously removed.

Thereafter, as shown in FIG. 9, the third resist pattern 23 is removed. The oxide-nitride film 16a and the silicon oxide film 13 of the low voltage withstanding area 11c are removed by etching with NH₄ F, thereby exposing the surface of the p type silicon substrate 11 of the low voltage withstanding area 11c.

Next, as shown in FIG. 10, a silicon oxide film 24 having a thickness of about 120 angstroms to be used as a gate insulating film of a low voltage withstanding element is formed on the surface of the exposed p type silicon substrate 11. At this time, a silicon oxide film 24a is formed on the third polycrystalline silicon film 22 of the cell area 11a, and a silicon oxide film 24b is formed on the first polycrystalline silicon film 14 of the high voltage withstanding area 11b.

Thereafter, a fourth polycrystalline silicon film 25 having a thickness about 1000 angstroms is deposited on the silicon oxide films 24, 24a and 24b and the fifth and sixth element separation insulating films 12e and 12f.

Thereafter, as shown in FIG. 11, a fourth resist pattern 26 is formed on the fourth polycrystalline film 25 of the low voltage withstanding area 11c. Next, the resist pattern 25 is used as a mask to perform isotropic etching, whereby the fourth polycrystalline silicon films 25 of the cell area 11a and the high voltage withstanding area 11b are removed, respectively.

Thereafter, as shown in FIG. 12, the fourth resist pattern 26 is separated. Thereafter, the silicon oxide films 24a and 24b are separated with NH₄ F. Next, a fifth polycrystalline silicon film 27 is deposited on the first, third, and fourth polycrystalline silicon films 14, 22, 25.

By a polycrystalline silicon film 27, the cell area 11a, the withstanding high voltage area 11b, and the low voltage withstanding area 11c are connected.

Thereafter, the third and fifth polycrystalline silicon films 22 and 27 of the cell area 11, the first and fifth polycrystalline silicon films 14 and 27 of the high voltage withstanding area 11b and the fourth and fifth polycrystalline silicon films 25 and 27 of the low voltage withstanding area 11c are respectively doped by phosphorus diffusion.

Thereafter, as shown in FIG. 13, a tungsten silicide film 28 is formed on the fifth polycrystalline silicon film 27 by sputtering. Next, a gate electrode of the transistor is processed. Thereafter, an interlayer insulating film is formed by the same method as the manufacturing method of a conventional MOS integrated circuit. Next, a metallic wiring is formed, and thereafter, a passivation film is formed.

According to the first embodiment, the gate insulating film 13 of the high voltage withstanding area 11b is first formed, and the gate insulating film 16 of the cell area 11a is next formed.

In other words, first, the gate insulating film 13 of the high voltage withstanding area 11b is formed on the surface of the p type silicon substrate 11. Then, the first polycrystalline silicon film 14 is formed on the gate insulating film 13 and the third to sixth element separation insulating films 12c to 12f.

Then, the polycrystalline silicon film 14 is used as a mask, and the silicon oxide film 13 of the cell area 11a is removed by etching with NH₄ F. Due to this, in removing by etching with NH₄ F, the third and fourth element separation insulating films 12c and 12d are not etched with NH₄ F.

Therefore, since the element separation insulating films 12c and 12d of the high voltage withstanding area 11b are not thinned, there is not a problem in which a reverse field voltage is lowered, and a required high voltage can be provided to the high voltage withstanding area 11b.

Also, the ONO layer film layer 21, which is used as an insulating film between the floating gate of the cell transistor and the control gate of the cell transistor is formed. Thereafter, the third polycrystalline silicon film 22 is continuously deposited on the ONO layer film 21, and the third resist pattern 23 is formed on the polycrystalline silicon film 22.

Due to this, unlike the conventional manufacturing method, the resist is not directly applied onto the ONO layer film 21. Therefore, the ONO layer film 21 is not polluted by the resist, and the film quality of the ONO layer film 21 is not deteriorated. As a result, insulation breakage of the nonvolatile semiconductor memory device, and the deterioration of data storing characteristics can be prevented. Also, reliability of the memory cell can be improved.

Also, unlike the conventional manufacturing method, the gate insulating film of the high voltage withstanding area is not formed after forming the gate insulating film of the cell area. First, the gate insulating film 13 of the high voltage withstanding area 11b is formed. Thereafter, the gate insulating film 16 of the cell area 11a is formed. Due to this, the process of separating the oxide-nitride-oxide film for the p type silicon substrate 11 in the high voltage withstanding area 11b is not needed. As a result, unlike the conventional manufacturing method, no white ribbon is left on the surface of the p type silicon substrate 11 of the high voltage withstanding area 11b. Therefore, voltage resistance to the gate insulating film of the high voltage withstanding area 11b is not deteriorated, and the reduction of yield due to the insulation breakage can be prevented.

Moreover, in order to control a threshold value of the transistor of the low voltage withstanding area 11c as required, impurity material can be introduced without providing a process of forming a new photoresist. In other words, after the process of etch-removing the silicon oxide film 13 and the oxide-nitride film 16a shown in FIG. 8, if impurity material is implanted to the p type silicon substrate 11 using that the third resist pattern 23 of the cell area 11a and the first polycrystalline silicon film 14 of the high voltage withstanding area 11b are used as masks, impurity material can be introduced to only the p type silicon substrate 11 of the low voltage withstanding area 11c. Therefore, it is possible to constitute a transistor, which is suitable for obtaining miniaturization and high performance, and increases in the manufacturing cost may be low.

In the above-mentioned first embodiment, an oxide-nitride film 16 having a good film quality as a gate insulating film is used as a gate insulating film in the cell area la. However, a silicon oxide film can be used as a gate insulating film in the cell area 11a. If oxide-nitride film 16 is used as a gate insulating film, leakage current in the low voltage area can be reduced. In terms of this point, reliability of the device can be improved. In contrast, if the silicon oxide film is used as a gate insulating film, stress between the element separation insulating films formed of the silicon oxide film can be relaxed. In terms of this point, reliability of the device can be improved.

FIG. 1 and FIGS. 14 to 20 are cross sectional views showing a method for manufacturing a nonvolatile semiconductor memory device of a second embodiment of the present invention. The same reference numerals are added to the portions common to the first embodiment.

First, after the process shown in FIG. 1, as shown in FIG. 14, a silicon oxide film 13, serving as a gate insulating film of the high voltage withstanding area 11b and having a thickness of about 250 angstroms, is formed on the surface of the p type silicon substrate 11 positioned among first to sixth separation insulating films 12a to 12f.

Thereafter, a first polycrystalline silicon film 31 having a thickness of about 1200 angstroms is deposited on the first to sixth element separation insulating films 12a to 12f and the silicon oxide film 13 by LPCVD. The first polycrystalline silicon film 31 constitutes the gate electrode.

Next, as shown in FIG. 15, a first resist pattern 15 is formed on the first polycrystalline silicon film 31 by lithography, and the resist is positioned on each of the high voltage withstanding area 11b, and the low voltage withstanding area 11c. Then, the first resist pattern 15 is used as a mask to perform isotropic etching, thereby removing the first polycrystalline silicon film 31 from the cell area 11a.

Thereafter, as shown in FIG. 16, the first resist pattern is removed. Thereafter, the silicon oxide film 13 is removed from the cell area hla by etching using NH₄ F, thereby exposing a surface of the p type silicon substrate 11.

As shown in FIG. 17, an oxide-nitride film 16 having a thickness of about 100 angstroms to serve as a gate insulating film of the cell area 11a is formed on the surface of the exposed p type silicon substrate 11. At this time, the oxide-nitride film 16a is formed on the first polycrystalline silicon film 31 of the high voltage withstanding area 11b, and the oxide-nitride film 16b is formed on the first polycrystalline silicon film 31 of the low voltage withstanding area 11c. Then, the second polycrystalline silicon film 17 having a thickness of about 1000 angstroms to serve as a floating gate of the cell area 11a is deposited on the oxide-nitride films 16, 16a, and 16b, and the first and second element separation insulating films 12a and 12b. Thereafter, phosphorus is doped to the second polycrystalline silicon film 17 by phosphorus diffusion.

Thereafter, as shown in FIG. 18, a second resist pattern 18 is formed on the second polycrystalline silicon film 17. The second resist pattern 18 is positioned at the area 19 where the floating gate of the cell transistor is formed and on the high voltage withstanding area 11b. Thereafter, the second resist pattern 18 is used as a mask to perform etching, whereby the second polycrystalline silicon film 17 on each of a floating gate separation area 20 of the cell area 11a and the low voltage withstanding area 11c is removed.

Next, as shown in FIG. 19, the second resist pattern 18 is removed. Then, as an insulating film between the floating gate of the cell transistor and the control gate of the cell transistor, for example, an ONO (oxide-nitride-oxide) layer film 21 is formed on the second polycrystalline silicon film 17 of the cell area 11a. At this time, the ONO layer film 21a is formed on the second polycrystalline silicon film 17 of the high voltage withstanding area 11b, and the ONO layer film 21b is formed on the first polycrystalline silicon film 14 of the low voltage withstanding area 11c. Thereafter, a third polycrystalline silicon film 22 having a thickness about 1000 angstroms is deposited on the ONO layer films 21, 21a and 21b.

Thereafter, as shown in FIG. 20, a third resist pattern 23 is formed on the third polycrystalline silicon film 22 of the cell area 11a. Thereafter, the resist pattern 23 is used as a mask to perform isotropic etching, so that the third polycrystalline silicon films 22 of the high voltage withstanding area 11b and the low voltage withstanding area 11c are simultaneously removed.

Next, the third resist pattern 23 is used as a mask to perform anisotropic etching, thereby removing the ONO layer films 21a and 21b. Thereafter, the resist pattern 23 is used as a mask to perform etching, so that the second polycrystalline silicon film 17 of the high voltage withstanding area 11b and the first polycrystalline silicon film 31 of the low voltage withstanding area 11c are simultaneously removed. Next, the third resist pattern 23 and the first polycrystalline silicon film 31 are used as masks, and, for example, boron 32 is implanted to the p type silicon substrate 11 of the low voltage withstanding area 11c in a state that an acceleration voltage is 20 keV and an amount of dose is about 1×10¹² cm⁻².

The above-mentioned second embodiment can obtain the same advantage as the first embodiment.

Moreover, the thickness of the first polycrystalline silicon film 31 is formed to be thicker than that of the case of the first embodiment. Due to this, in ion-implanting boron 32 in the state that the third resist pattern 23 and the first polycrystalline silicon film 31 of the high voltage withstanding area 11b are used as masks, there does not occur a case in which impurity material, that is, boron 32 is partially passed through the first polycrystalline silicon film 31 and reaches to the p type silicon substrate 11 of the high voltage withstanding area 11b. Therefore, it is possible to prevent variation of the threshold value of the transistor of the high voltage withstanding area 11b generated when the impurity material is implanted to the p type silicon substrate 11 of the high voltage withstanding area 11b.

FIGS. 1, 2, 21 to 27 are cross sectional views showing a method for manufacturing a nonvolatile semiconductor memory device of a third embodiment of the present invention. The same reference numerals are added to the portions common to the first embodiment, and only the different portions will be explained.

After the process shown in FIGS. 1 and 2, as shown in FIG. 21, a silicon oxide film 33 having a thickness of about 200 angstroms is formed on the first polycrystalline silicon film 14 by LPCVD.

Next, a first resist pattern 15 as shown in FIG. 22 is formed on the silicon oxide film 33 by lithography, and the resist is positioned on each of the high voltage withstanding area 11b and the low voltage withstanding area 11c. Thereafter, the first resist pattern is used as a mask to perform etching, thereby removing the silicon oxide film 33 of the cell area 11a. Next, the first resist pattern is used as a mask to perform etching, thereby removing the first polycrystalline silicon film 14 of the cell area 11a.

Next, as shown in FIG. 23, the first resist pattern 15 is removed. Thereafter, the silicon oxide film 13 is removed from the cell area 11a by etching using NH₄ F, thereby exposing a surface of the p type silicon substrate 11.

Thereafter, as shown in FIG. 24, an oxide-nitride film 16 having a thickness of about 100 angstroms to serve as a gate insulating film of the cell area 11a is formed on the surface of the exposed p type silicon substrate 11. Then, a second polycrystalline silicon film 17 having a thickness of about 1000 angstroms to serve as a floating gate of the cell area 11a is deposited on the oxide-nitride films 16 and the silicon oxide film 33, and the first and second element separation insulating films 12a and 12b. Thereafter, phosphorus is doped to the second polycrystalline silicon film 17 by phosphorus diffusion.

Then, as shown in FIG. 25, a second resist pattern 18 is formed on the second polycrystalline silicon film 17. The second resist pattern 18 is positioned at an area 19 where the floating gate of the cell transistor is formed and on the high voltage withstanding area 11b. Thereafter, the second resist pattern 18 is used as a mask to perform etching whereby the second polycrystalline silicon film 17 on each of a floating gate separation area 20 of the cell area 11a and the low voltage withstanding area 11c is removed.

Thereafter, as shown in FIG. 26, the second resist pattern 18 is removed. Then, as an insulating film between the floating gate of the cell transistor and a control gate, for example, an ONO (oxide-nitride-oxide) layer film 21 is formed on the second polycrystalline silicon film 17 of the cell area 11a. At this time, an ONO layer film 21a is formed on the second polycrystalline silicon film 17 of the high voltage withstanding area 11b, and an ONO layer film 21b is formed on the first polycrystalline silicon film 14 of the low voltage withstanding area 11c. Thereafter, a third polycrystalline silicon film 22 having a thickness about 1000 angstroms is deposited on the ONO layer films 21, 21a and 21b.

Next, as shown in FIG. 27, a third resist pattern 23 is formed on a third polycrystalline silicon film 22 of the cell area 11a. Thereafter, the resist pattern 23 is used as a mask to perform isotropic etching, so that the third polycrystalline silicon films 22 of the high voltage withstanding area 11b and the low voltage withstanding area 11c are simultaneously removed.

Next, the third resist pattern 23 is used as a mask to perform anisotropic etching, thereby removing the ONO layer films 21a and 21b. Thereafter, the resist pattern 23 is used as a mask to perform etching, so that the second polycrystalline silicon film 17 of the high voltage withstanding area 11b and the first polycrystalline silicon film 14 of the low voltage withstanding area 11c are simultaneously removed.

Next, the third resist pattern 23, the first polycrystalline silicon film 31, and the silicon oxide film 33 having a thickness of about 200 angstroms are used as masks, and impurity material is introduced to the p type silicon substrate 11 of the low voltage withstanding area 11c.

The above-mentioned third embodiment can obtain the same advantage as the second embodiment.

In other words, in the process shown in FIG. 32, both first polycrystalline silicon film 14 and silicon oxide film 33 are used to introduce impurity material to the p type silicon substrate 11 of the low voltage withstanding area 11c. Due to this, impurity material can be prevented from being partially passed through the first polycrystalline silicon film 14. As a result, impurity material can be prevented from being implanted to the p type silicon substrate 11 of the high voltage withstanding area 11b.

It is apparent that, in this invention, a wide range of different working modes can be formed based on the invention without deviating from the spirit and scope of the invention. This invention is not restricted by its specific working modes except being limited by the appended claims. 

What is claimed is:
 1. A semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed on said semiconductor substrate to define a first element region; a low withstand voltage MOS transistor formed in said first element region, said low withstand voltage MOS transistor having a first gate electrode coupled with a first power voltage; a second element separation insulating film formed on said semiconductor substrate to define a second element region, the second element separation insulating film having a thickness greater than a thickness of the first element separation insulating film; and a high withstand voltage MOS transistor formed in said second element region, said high withstand voltage MOS transistor having a second gate electrode coupled with a second power voltage higher than said first power voltage, a thickness of said second gate electrode being greater than a thickness of said first gate electrode.
 2. The semiconductor memory device of claim 1, wherein said low withstand voltage MOS transistor has a gate insulating film having a thickness of about 120 angstroms, and said high withstand voltage MOS transistor has a gate insulating film having a thickness of about 250 angstroms.
 3. The semiconductor device of claim 1, wherein the thickness of said first gate electrode is about 1000 angstroms and the thickness of said second gate electrode is about 1200 angstroms.
 4. The semiconductor memory device of claim 1, wherein the first element separation insulating film is formed at a periphery of the first element region, and the second element separation insulating film is formed at a periphery of the second element region.
 5. The semiconductor memory device of claim 1, further comprising:a first voltage node coupled to said low withstand voltage MOS transistor for supplying said first power voltage; and a second voltage node coupled to said high withstand voltage MOS transistor for supplying said second power voltage.
 6. The semiconductor memory device of claim 1, wherein the first element separation insulating film and the second element separation insulating film are each formed directly on the semiconductor substrate.
 7. A semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed on said semiconductor substrate to define a first element region; a second element separation insulating film formed on said semiconductor substrate to define a second element region; a low withstand voltage MOS transistor formed in said first element region, said low withstand voltage MOS transistor comprising a gate electrode to which a first power voltage is supplied and a first gate insulating film; and a high withstand voltage MOS transistor formed in said second element region, said high withstand voltage MOS transistor comprising a gate electrode to which a second power voltage is supplied and a second gate insulating film, said second power voltage being higher than said first power voltage, a thickness of said gate electrode of said high withstand voltage MOS transistor being greater than a thickness of said gate electrode of said low withstand voltage MOS transistor, and a thickness of said second gate insulating film being greater than a thickness of said first gate insulating film.
 8. The semiconductor memory device of claim 7, wherein the thickness of said gate electrode of said low withstand voltage MOS transistor is about 1000 angstroms and the thickness of said gate electrode of said high withstand voltage MOS transistor is about 1200 angstroms.
 9. The semiconductor memory device of claim 7, wherein a thickness of said first gate insulating film is about 120 angstroms and a thickness of said second gate insulating film is about 250 angstroms.
 10. The semiconductor memory device of claim 7, wherein the first element separation insulating film is formed at a periphery of the first element region, and the second element separation insulating film is formed at a periphery of the second element region.
 11. The semiconductor memory device of claim 7, further comprising:a first voltage node coupled to the gate electrode of said low withstand voltage MOS transistor for supplying said first power voltage; and a second voltage node coupled to the gate electrode of said high withstand voltage MOS transistor for supplying said second power voltage.
 12. A nonvolatile semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed on said semiconductor substrate to define a first element region, a first MOS transistor to which a first power voltage is applied being formed in said first element region; a second element separation insulating film formed on said semiconductor substrate to define a second element region, a second MOS transistor being formed in said second element region, a second power voltage higher than the first power voltage being applied to said second MOS transistor, a thickness of said second element separation insulating film being greater than a thickness of said first element separation film; a first insulating film of said first MOS transistor formed on said first element region; a second insulating film of said second MOS transistor formed on said second element region; a first polysilicon film formed on said first insulating film for forming part of a gate electrode of said first MOS transistor; and a second polysilicon film formed on said second insulating film for forming part of a gate electrode of said second MOS transistor, a thickness of said second polysilicon film being greater than a thickness of said first polysilicon film.
 13. The nonvolatile semiconductor memory device according to claim 12, wherein a thickness of said first insulating film is about 120 angstroms and a thickness of said second insulating film is about 250 angstroms.
 14. The nonvolatile semiconductor memory device according to claim 12, wherein the thickness of said first polysilicon film is about 1000 angstroms and the thickness of said second polysilicon film is about 1200 angstroms.
 15. The semiconductor memory device of claim 12, wherein the first element separation insulating film is formed at a periphery of the first element region, and the second element separation insulating film is formed at a periphery of the second element region.
 16. The nonvolatile semiconductor memory device of claim 12, further comprising:a first voltage node coupled to said first MOS transistor for supplying said first power voltage; and a second voltage node coupled to said second MOS transistor for supplying said second power voltage.
 17. The semiconductor memory device of claim 12, wherein the first element separation insulating film and the second element separation insulating film are each formed directly on the semiconductor substrate.
 18. A nonvolatile semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed directly on said semiconductor substrate to define a first element region, a first MOS transistor to which a first power voltage is applied being formed in said first element region; a second element separation insulating film formed directly on said semiconductor substrate to define a second element region, a second MOS transistor being formed in said second element region, a second power voltage higher than the first power voltage being applied to said second MOS transistor, a thickness of said second element separation insulating film being greater than a thickness of said first element separation insulating film; a third element separation insulating film formed directly on said semiconductor substrate to define a third element region, a cell transistor being formed in said third element region, a third power voltage lower than the second power voltage being applied to said cell transistor, a thickness of said third element separation insulating film being less than a thickness of said second element separation film; a first gate insulating film of said first MOS transistor formed directly on said semiconductor substrate in said first element region; a second gate insulating film of said second MOS transistor formed directly on said semiconductor substrate in said second element region; a third gate insulating film of said cell transistor formed directly on said semiconductor substrate in said third element region; a first polysilicon film formed directly on said first gate insulating film and forming at least a portion of a gate electrode of said first MOS transistor; a second polysilicon film formed directly on said second gate insulating film and forming at least a portion of a gate electrode of said second MOS transistor, a thickness of said second polysilicon film being greater than a thickness of said first polysilicon film; a third polysilicon film formed directly on said third gate insulating film and forming at least a portion of a floating gate of said cell transistor; a fourth gate insulating film formed directly on said third polysilicon film; and a fourth polysilicon film formed directly on said fourth gate insulating film and forming at least a portion of a control gate of said cell transistor.
 19. The nonvolatile semiconductor memory device of claim 18, wherein the first element separation insulating film is formed at a periphery of the first element region, the second element separation insulating film is formed at a periphery of the second element region, and the third element separation insulating film is formed at a periphery of the third element region.
 20. A semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed directly on said semiconductor substrate to define a first element region; a low withstand voltage MOS transistor formed in said first element region, said low withstand voltage MOS transistor having a first gate electrode supplied with a first power voltage and having a first gate insulating film formed directly on said semiconductor substrate; a second element separation insulating film formed directly on said semiconductor substrate to define a second element region, the second element separation insulating film having a thickness greater than a thickness of the first element separation insulating film; and a high withstand voltage MOS transistor formed in said second element region, said high withstand voltage MOS transistor having a second gate electrode supplied with a second power voltage higher than said first power voltage and having a second gate insulating film formed directly on said semiconductor substrate, a thickness of said second gate electrode being greater than a thickness of said first gate electrode.
 21. A semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed directly on said semiconductor substrate to define a first element region; a second element separation insulating film formed directly on said semiconductor substrate to define a second element region; a low withstand voltage MOS transistor formed in said first element region, said low withstand voltage MOS transistor comprising a gate electrode to which a first power voltage is supplied and a first gate insulating film; and a high withstand voltage MOS transistor formed in said second element region, said high withstand voltage MOS transistor comprising a gate electrode to which a second power voltage is supplied and a second gate insulating film, said second power voltage being higher than said first power voltage, a thickness of said gate electrode of said high withstand voltage MOS transistor being greater than a thickness of said gate electrode of said low withstand voltage MOS transistor, and a thickness of said second gate insulating film being greater than a thickness of said first gate insulating film.
 22. A nonvolatile semiconductor memory device comprising:a semiconductor substrate; a first element separation insulating film formed directly on said semiconductor substrate to define a first element region, a first MOS transistor to which a first power voltage is applied being formed in said first element region; a second element separation insulating film formed directly on said semiconductor substrate to define a second element region, a second MOS transistor being formed in said second element region, a second power voltage higher than the first power voltage being applied to said second MOS transistor, a thickness of said second element separation insulating film being greater than a thickness of said first element separation film; a first gate insulating film of said first MOS transistor formed directly on said semiconductor substrate in said first element region; a second insulating film of said second MOS transistor formed directly on said semiconductor substrate in said second element region; a first polysilicon film formed directly on said first gate insulating film and forming at least a portion of a gate electrode of said first MOS transistor; and a second polysilicon film formed directly on said second gate insulating film and forming at least a portion of a gate electrode of said second MOS transistor, a thickness of said second polysilicon film being greater than a thickness of said first polysilicon film.
 23. A semiconductor device comprising:a semiconductor substrate; a first element separation insulating film formed on said semiconductor substrate to define a first element region; a second element separation insulating film formed on said semiconductor substrate to define a second element region; a low withstand voltage device formed in said first element region, said low withstand voltage device having a first gate electrode; and a high withstand voltage device formed in said second element region, said high withstand voltage device having a second gate electrode, a thickness of said second gate electrode being greater than a thickness of said first gate electrode.
 24. The semiconductor device of claim 23, wherein said low withstand voltage device includes a low withstand voltage MOS transistor, said first gate electrode being a gate electrode of said low withstand voltage MOS transistor, and said high withstand voltage device includes a high withstand voltage MOS transistor, said second gate electrode being a gate electrode of said high withstand voltage MOS transistor.
 25. The semiconductor device of claim 23, wherein said first element separation insulating film and said second element separation insulating film are each formed directly on the semiconductor substrate.
 26. The semiconductor device of claim 23, wherein said first element separation insulating film is formed at a periphery of said first element region, and said second element separation insulating film is formed at a periphery of said second element region. 